1. Technical Field
The present disclosure relates to a wiring substrate and a semiconductor device.
2. Description of the Related Art
A wiring substrate including solder bumps that are connected with an electric component such as a semiconductor chip has been known (see JP-A-10-326965 and JP-A-2004-200412 for example). In addition, as a method of producing such a wiring substrate, the following method has been known.
First, a structural body illustrated in FIG. 6A, for example, is prepared. This structural body is configured of connection pads 80P to be connected to build-up wirings (not illustrated), the connection pads 80P being formed on an interlayer insulating layer 81, and a solder resist layer 82 having opening portions 82X that are positioned above the corresponding connection pads 80P. Next, a seed layer 83 is formed so as to cover an upper surface of the solder resist layer 82 including inner surfaces of the opening portions 82X, and connection pads 80P exposed through the opening portions 82X. Then, a resist layer 84 is formed on the seed layer 83. The resist layer 84 includes opening portions 84X, each of which has a diameter larger than a diameter of the opening portions 82X.
Next, in a process illustrate in FIG. 6B, a solder plating method (for example, a Sn—Cu electrolytic plating method), which uses the seed layer 83 as a power feeding layer, is performed, using the resist layer 84 as a plating mask, thereby to form solder plating layers 85 on the seed layer 83 that has been exposed through the opening portions 84X. Subsequently, in a process illustrated in FIG. 6C, the resist layer 84 illustrated in FIG. 6B and unnecessary parts of the seed layers 83 below the resist layer 84 are removed. Then, the solder plating layers 85 are reflow-heated, so that the solder plating layer 85 are melted and thus bonded with the corresponding connection pads 80P. With this, solder bumps 86 protruding from the upper surface of the solder resist layer 82 are obtained, as illustrated in FIG. 6D.
In recent years, along with advancement in a semiconductor chip technology, a pitch of the connection pads in the wiring substrate has been made narrower. In addition, the solder bumps 86 need to be sufficiently high (for example, 40 μm or higher) from the upper surface of the solder resist layer 82 in the wiring substrate, in order to accomplish sufficient reliability of electric connection with the semiconductor chip. However, as the pitch of the connection pads 80P is narrower, it becomes difficult to form higher solder bumps 86. Namely, when the solder plating layers 85 are formed thicker in order to ensure sufficient heights of the solder bumps 85, a resultant solder bump tends to contact an adjacent solder bump, as solder bumps 85A illustrated in FIG. 7. Such solder bumps 85A cause short circuits. Therefore, it is difficult to form the high solder bumps 86, and to realize reliable mounting of the semiconductor chips on the wiring substrate.